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ADT7467
Miscellaneous Functions
Operating from 3.3 V Standby
The ADT7467 has been specifically designed to operate
from a 3.3 V STANDBY supply. In computers that support
S3 and S5 states, the core voltage of the processor is lowered
in these states. If using the dynamic T MIN mode, lowering
the core voltage of the processor changes the CPU
temperature and changes the dynamics of the system under
dynamic T MIN control. Likewise, when monitoring
THERM, the THERM timer should be disabled during these
states.
Dynamic T MIN Control Register 1 (0x36) <1> V CCP LO = 1
When the power is supplied from 3.3 V STANDBY and
the V CCP voltage drops below the V CCP low limit, the
following occurs:
1. Status Bit 1 (V CCP ) in Interrupt Status Register 1
is set.
2. SMBALERT is generated if enabled.
3. THERM monitoring is disabled. The THERM
timer should hold its value prior to the S3 or S5
state.
Power-On Default
When the ADT7467 is powered up, it polls the V CCP
input.
If V CCP stays below 0.75 V (the system CPU power rail
is not powered up), the ADT7467 assumes the functionality
of the default registers after the ADT7467 is addressed via
any valid SMBus transaction.
If V CC goes high (the system processor power rail is
powered up), a fail-safe timer begins to count down. If the
ADT7467 is not addressed by a valid SMBus transaction
before the fail-safe timeout (4.6 sec) lapses, the ADT7467
drives the fans to full speed. If the ADT7467 is addressed by
a valid SMBus transaction after this point, the fans stop and
the ADT7467 assumes its default settings and begins normal
operation.
If V CCP goes high (the system processor power rail is
powered up), a fail-safe timer begins to count down. If the
ADT7467 is addressed by a valid SMBus transaction before
the fail-safe timeout (4.6 sec) lapses, the ADT7467 operates
normally, assuming the functionality of all default registers.
See the flow chart in Figure 47.
4. Dynamic T MIN control is disabled. This prevents
T MIN from being adjusted due to an S3 or S5 state.
5. The ADT7467 is prevented from shutting down.
Once the core voltage, V CCP , goes above the V CCP low
limit, everything is re-enabled and the system resumes
normal operation.
XNOR Tree Test Mode
The ADT7467 includes an XNOR tree test mode. This
mode is useful for in-circuit test equipment at board-level
Y
ADT7467 is Powered Up
Has the ADT7467 Been
Accessed by a Valid
SMBUS Transaction?
N
Is V CCP Above 0.75 V?
Y
Start Fail ? Safe Timer
N
Check V CCP
testing. By applying stimulus to the pins included in the
XNOR tree, it is possible to detect opens or shorts on the
system board.
Figure 46 shows the signals that are exercised in the
XNOR tree test mode. The XNOR tree test is invoked by
setting Bit 0 (XEN) of the XNOR tree test enable register
(0x6F).
Y
Has the ADT7467 Been
Accessed by a Valid
SMBUS Transaction?
N
Fail ? Safe Timer Elapses
After the Fail ? Safe
Timeout
TACH1
TACH2
Has the ADT7467 Been
Accessed by a Valid
SMBUS Transaction?
N
Run the Fans to
Full Speed
TACH3
TACH4
PWM2
Y
Start Up the
ADT7467 Normally
Has the ADT7467 Been
Accessed by a Valid
SMBUS Transaction?
Y
Switch Off Fans
N
PWM3
PWM1/XTO
Figure 47. Power-On Flowchart
Figure 46. XNOR Tree Test
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